An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

The DBC : Processing Scienti

We present the Distributed Batch Controller (DBC), a system built to support batch processing of large scientiic datasets. The DBC implements a federation of autonomous workstation pools, which may be widely-distributed. Individual batch jobs are executed using idle workstations in these pools. Input data are staged to the pool before processing begins. We describe the architecture and implemen...

A 12 bit 2.9 GS/s DAC With IM3 60 dBc Beyond 1 GHz in 65 nm CMOS

A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an dBc beyond 1 GHz while driving a 50 load with an output swing of 2.5 and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previo...

Database Programming with DBC and JAVA

An All-digital UWB Transmitter in 90-nm CMOS

Pulsed ultra-wideband (UWB) transceivers offer the potential for ultra-low-energy/bit operation because the signals are inherently duty-cycled. By eliminating components with long startup times, such as a phase-locked loop, all components in a pulsed-UWB transceiver can be disabled during the interval between pulses. This work focuses on an all-digital, pulsed-UWB transmitter that requires no a...

A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop

A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6m CMOS technology is developed for the Wireless Integrated Network Sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain ( VCO) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in or...